1. Field of the Invention
The present invention generally relates to a method of manufacturing a semiconductor device. More particularly, the present invention generally relates to a method of manufacturing a semiconductor device in which a silicide blocking layer and a spacer are simultaneously formed prior to an impurity implantation.
A claim of priority is made to Korean Patent Application No. 2003-100232 filed on Dec. 30, 2003, the contents of which are herein incorporated by reference in their entirety.
2. Description of the Related Art
As semiconductor devices have become more integrated, the size of each unit device has gradually reduced. Thus, the interval between each unit devices has also gradually reduced. The reduction in both size and interval of each unit device has improved the manufacturing yield of the semiconductor devices, but has also caused manufacturing problems.
For example, a higher degree of integration leads to the reduction in a channel length in a metal-oxide silicon transistor, and the reduction causes a short channel effect such as a punch through and a threshold voltage reduction. To improve the short channel effect, a low temperature heat treatment process has been used, which prevents lateral diffusion of implanted impurities in a lightly doped source/drain region.
The higher degree of integration also leads to an increase in sheet resistance by conductive structures such as a gate electrode and a source/drain region, which in turn, reduces the operational speed of the semiconductor devices. Conventionally, a silicide layer has been formed on the conductive structures to reduce the sheet resistance.
However, the low temperature heat treatment process is incompatible with the silicidation process. Conventionally, if a substrate contains both a resistance device without a silicide layer and a transistor with a silicide layer, the transistor is usually formed prior to the formation of the resistance device, and the resistance device generally operate in an analogue mode. The transistor is formed on a first region, and the first region is formed on a source/drain region. The resistance device is formed on a second region, and a silicide blocking layer is formed on the second region. The silicide layer is formed on the conductive structures in the first region, and formed only on a gate structure and source/drain structure of the transistor in the second region.
In the above described process, the silicide blocking layer is generally formed at a high temperature to enhance the diffusion of the impurities into the source/drain region. In other words, the silicidation process is generally performed at a high temperature.
To solve the above described problem, for example, U.S. Pat. No. 5,883,010 discloses using spacers instead of a silicide blocking layer to protect a portion of the substrate not having the silicide layer during a silicidation process. A spacer oxide layer pattern is formed at the same time when the gate spacer is formed to prevent the silicide layer from being coated on the portion of the substrate without the silicide layer.